Phase shifters may be classified into several types with regards to the configuration. Among these are a line-switching type where 50 Ω(ohm) lines having different lengths are connected using two SPDT (Single-Pole Dual Throw) switches (single-pole two-contact switches), and an electrical length difference between both of the lines obtained by switch changeover is used as a phase shift amount, and an HPF/LPF switching type where a plurality of lumped-constant inductors and capacitors, and SPDT switches are combined, and a phase difference caused by electrical switching between an LC type low-pass filter (LPF) and an LC high-pass filter (HPF) is used. There are also some types of switch units including a series/shunt type where a series FET (Field Effect Transistor) and a shunt FET are used concurrently and a resonant type where an inductor is connected in parallel with an FET. As will be described later, the present invention employs switches of the resonant type and a phase shifter of the HPF/LPF switching type, among these types.
In the case of filters as shown in FIG. 9, when an LPF is on, the following expression holds:
                              S          21                =                  2                                    2              ⁢                              (                                  1                  -                                                            B                      N                                        ⁢                                          X                      N                                                                      )                                      +                          j              ⁡                              (                                                      B                    N                                    +                                      2                    ⁢                                          X                      N                                                        -                                                            B                      N                                        ⁢                                          X                      N                      2                                                                      )                                                                        (        1        )            
In the above expression (1), XN and BN denote a normalized reactance and a normalized susceptance, respectively.
A phase of the pass characteristic S21 is delayed. When the delay is indicated by Φ1, the delay Φ1 is given by the following expression (2):
                              Φ          1                =                              tan                          -              1                                ⁡                      [                          -                                                                    B                    N                                    +                                      2                    ⁢                                          X                      N                                                        -                                                            B                      N                                        ⁢                                          X                      N                      2                                                                                        2                  ⁢                                      (                                          1                      -                                                                        B                          N                                                ⁢                                                  X                          N                                                                                      )                                                                        ]                                              (        2        )            
Conversely, when an FET on an HPF side in an SPDT switch unit is on, XN is substituted into XN, and BN is substituted into BN, and the following expression is thereby obtained:
                              S          21                =                  2                                    2              ⁢                              (                                  1                  -                                                            B                      N                                        ⁢                                          X                      N                                                                      )                                      +                          j              ⁡                              (                                                      -                                          B                      N                                                        -                                      2                    ⁢                                          X                      N                                                        +                                                            B                      N                                        ⁢                                          X                      N                      2                                                                      )                                                                        (        3        )            
In this case, the phase of the pass characteristic S21 is advanced, and this advance is indicated by Φ2.
                              Φ          2                =                              tan                          -              1                                ⁡                      [                          -                                                                    -                                          B                      N                                                        -                                      2                    ⁢                                          X                      N                                                        +                                                            B                      N                                        ⁢                                          X                      N                      2                                                                                        2                  ⁢                                      (                                          1                      -                                                                        B                          N                                                ⁢                                                  X                          N                                                                                      )                                                                        ]                                              (        4        )            
A phase shift amount is defined by a difference ΔΦ between the phases Φ1 and Φ2, and is expressed by the following expression (5):
                    ΔΦ        =                                            Φ              1                        -                          Φ              2                                =                      -                                          tan                                  -                  1                                            ⁡                              [                                  -                                                                                    B                        N                                            +                                              2                        ⁢                                                  X                          N                                                                    -                                                                        B                          N                                                ⁢                                                  X                          N                          2                                                                                                            2                      ⁢                                              (                                                  1                          -                                                                                    B                              N                                                        ⁢                                                          X                              N                                                                                                      )                                                                                            ]                                                                        (        5        )            
When the HPF side is turned on and an LPF side is turned off in such a phase shifter, and when an inductor in the switch unit is formed of a low-resistance interconnect and a parasitic resistance of the inductor is small, a rise and fall (such as an irregularity or a bump) caused by resonance is generated in a frequency characteristic of the phase shift amount.
This deteriorates an RMS (root mean square) phase shift error indicated by the following expression:
                              RMS          ⁢                                          ⁢          phase          ⁢                                          ⁢          shift          ⁢                                          ⁢          amount                =                                            ∑                              i                =                1                            n                        ⁢                                                            (                                      ΔΦ                    -                                          Φ                      0                                                        )                                2                            n                                                          (        6        )            where n indicates the number of frequency points, and Φ0 indicates a given phase shift amount.
FIG. 10 is a diagram showing a configuration of a phase shifter disclosed in Patent Document 1. As shown in FIG. 10, this phase shifter is formed by arranging two SPDT switches 11c and 11d in an input unit and an output unit, respectively, and connecting a high-pass filter (HPF) 12 and a low-pass filter (LPF) 13 between the SPDT switches 11c and 11d. In each of the SPDT switches 11c and 11d, each inductor is connected in parallel with each FET. When one of two FETs Q1 and Q3 on a side of the HPF 12 and two FETs Q5 and Q7 on a side of the LPF 13 are turned on due to gate biasing, the other of the two FETs Q1 and Q3 on the side of the HPF 12 and the two FETs Q5 and Q7 on the side of the LPF 13 are turned off. In order to more improve cutoff characteristics of the FETs that are turned off and improve pass characteristics of the FETs that are turned on, inductors L21, L22, L23 and L24 are connected in parallel with the FETs Q1, Q5, Q3, and Q7, respectively. Parallel resonance is thereby produced in a desired band. Incidentally, IN, 10a, C10, L10, SPDTSW. C11, L11, C12, L12, C13, L13, C14, L14, 10b, and OUT comprise input, output, LC circuits, capacitors, inductors, and SPDT switches, as conventionally understood in the art; however, a more detailed description of those components is not necessary to understand the present invention.
Further, it is necessary to insert a capacitor in series with each inductor in order to measure a DC characteristic of each FET. A layout configuration where the capacitor is connected in series with the inductor is usually a layout where an inductor (a spiral inductor) 22 is made to have a non-close-packed structure so as to enhance a Q factor and further, an MIM (Metal Insulator Metal) capacitor 21 is arranged outside the inductor 22, as shown in FIG. 11. FIG. 11 shows a layout of an LC series-connected monolithic filter described as a related art in Patent Document 2. The capacitor 21 and the inductor (spiral inductor) 22 are two-dimensionally arranged on a semiconductor substrate.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2006-19823A
[Patent Document 2] JP Patent Kokai Publication No. JP-A-7-66043
[Non-patent Document 1] Shiban K. Koul and Bharathi Bhat, “Microwave and Milimeter Wave Phase Shifters Volume II Semiconductor and Delay Line Phase Shifters”, pp 412-413, Artech House, 1991
The disclosures of the above-mentioned Patent Documents 1 and 2, and Non-Patent Document 1 are herein incorporated by reference thereto. The following analysis is given by the present invention.
In the configuration in FIG. 10, when one of the two FETs Q1 and Q3 on the side of the HPF 12 and the two FETs Q5 and Q7 on the side of the LPF 13 are turned on due to gate biasing, the other of the two FETs Q1 and Q3 on the side of the HPF 12 and the two FETs Q5 and Q7 on the side of the LPF 13 are turned off, thereby performing switching between the two FETs Q1 and Q3 and the two FETs Q5 and Q7 for use. In order to improve the pass characteristics of the FETs which are turned on, the inductors are connected in parallel with the FETs that are turned off, respectively, thereby producing parallel resonance in a desired band and bringing the FETs that are turned off into a high-impedance state. The cutoff characteristics of the FETs that are turned off are improved more. This allows a desired insertion loss and a desired phase shift amount.
In the configuration in FIG. 11, the non-close-packed inductor (spiral inductor) 22 and the MIM (Metal Insulator Metal) capacitor 21 having an area, of which an impedance becomes substantially zero in a desired band, provided on the semiconductor substrate, are connected in series. A DC current that flows through the inductor is blocked, and the DC characteristic of the FET can be measured. The DC characteristic of the FET in an on state can be approximated by resistance, while the DC characteristic of the FET on an off state can be approximated by capacitance.
An equivalent circuit of a phase shifter where a parasitic capacitance of each inductor is arranged in series with the inductor in view of the parasitic capacitance of the inductor, an HPF side is turned on, and an LPF side is turned off is as shown in FIG. 12. In the phase shifter, a circuit where an HPF is connected between two sets of on-time switch units is connected to an input unit and an output unit. In the HPF, a shunt inductor L2 is arranged between two series capacitors C2. Then, a circuit where an LPF is connected between two sets of off-time switch units is connected to the input unit and the output unit. In the LPF, a shunt capacitor C3 is arranged between two series inductors L3. Each on-time switch unit includes a resistance R1 that equivalently indicates an FET in the on state, an inductor L1 connected in parallel with the resistance R1, and a parasitic resistance R2 of the inductor L1. Each off-time switch unit includes a capacitor C1 that equivalently indicates an FET in the off state, an inductor L1 connected in parallel with the capacitor C1, and a resistance component R2 of the inductor L1.
Impedance of the LPF side as seen from an input side will be derived in the below. Since this circuit is symmetrical with respect to the filter, an equivalent circuit as shown in FIG. 13 can substitute the LPF side in FIG. 12. When the inductor has a low resistance, and when R2 is approximated to zero, the following expression holds:
                    Z        =                  j          ⁡                      (                                                            ω                  ⁢                                                                          ⁢                                      L                    1                                                                    1                  -                                                            ω                      2                                        ⁢                                          L                      1                                        ⁢                                          C                      1                                                                                  +                              ω                ⁢                                                                  ⁢                                  L                  3                                            -                              2                                  ω                  ⁢                                                                          ⁢                                      C                    3                                                                        )                                              (        7        )                                Then        ,                                          Z                                =                                                    ω                ⁢                                                                  ⁢                                  L                  1                                                            1                -                                                      ω                    2                                    ⁢                                      L                    1                                    ⁢                                      C                    1                                                                        +                          ω              ⁢                                                          ⁢                              L                3                                      -                          2                              ω                ⁢                                                                  ⁢                                  C                  3                                                                                        (        8        )            
A resonant frequency ω0 in a parallel resonant circuit (refer to FIG. 14) where the inductor L1 and the resistance R2 connected in series is connected in parallel with the capacitance C1 is computed. Incidentally, “ω” as used in the present application represents the angular frequency in radians per second, for which ω=2πf holds.
An admittance Y is given by:
                    Y        =                                            1                                                R                  2                                +                                  j                  ⁢                                                                          ⁢                  ω                  ⁢                                                                          ⁢                                      L                    1                                                                        +                          jω              ⁢                                                          ⁢                              C                1                                              =                                                    R                2                                                              R                  2                  2                                +                                                      ω                    2                                    ⁢                                      L                    1                    2                                                                        +                          jω              ⁡                              (                                                      C                    1                                    -                                                            L                      1                                                                                      R                        2                        2                                            +                                                                        ω                          2                                                ⁢                                                  L                          1                          2                                                                                                                    )                                                                        (        9        )            Since resonance is produced when an imaginary part is zero, the resonant frequency ω0 becomes as follows:
                              ω          0                =                                            1                                                L                  1                                ⁢                                  C                  1                                                      -                                          R                2                2                                            L                1                2                                                                        (        10        )            
In view of this relationship, a condition that makes the resonant frequency ω0 constant is expressed by:
                              C          1                =                              L            1                                              R              2              2                        +                                          ω                0                2                            ⁢                              L                1                2                                                                        (        11        )            By substituting this equation (11) into the expression of |Z|, the computation is performed.
When f0=10 GHz (=ω0/2π), L1=1 nH, R2=0Ω, L3=0.03 nH, and C3=0.2 pF, it can be seen that impedance Z falls to approximately 0 ohms at 8.4 GHz, as shown in FIG. 15.
Inventors of the present invention have first found that though the LPF side in FIG. 12 should originally have a high impedance, the short circuit as described above is caused, so that a pass characteristic of the filter side which is turned on or the HPF side deteriorates and a phase shift amount also has a minute rise and fall (such as an irregularity or a bump) caused by resonance. This fact is not described in any document known to the inventors. Then, this causes deterioration of an RMS phase shift error.
In the layout where a capacitor is connected in series with an inductor so as to allow measurement of a DC characteristic of an FET, a capacitor 2 is laid out outside a non-close-packed inductor 1, as shown in FIG. 16.
In this layout configuration, a Q factor is high, as shown in a comparative example in FIG. 8 as a “related art”. Thus, an unwanted rise and fall caused by resonance is produced in a frequency characteristic of a phase shift amount.